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IBM says it has built the world’s first chip technology to push below one nanometer, a threshold the semiconductor industry has been edging toward for years as the physics of shrinking transistors grew harder to fight. The company unveiled the breakthrough on June 25, describing a transistor architecture at what it calls the 0.7 nanometer, or 7 angstrom, node, a scale where chip features approach the size of individual atoms. The announcement matters because the steady miniaturization that has driven computing for half a century has been running into a wall, and IBM is claiming a way over it.
The heart of the advance is a new structure the company calls nanostack, which it describes as the industry’s first three dimensional, nanosheet based transistor design. For decades chipmakers improved performance mainly by making transistors smaller and packing them closer together on a flat surface. That approach is reaching its limits, so nanostack changes direction by stacking transistors vertically and staggering them, using a method known as three dimensional sequential integration to fit more computing into the same footprint. Rather than only shrinking the parts, IBM is building upward, the same conceptual shift that let cities grow by adding floors instead of sprawling outward.
The numbers IBM put on the chip are striking. The company says nanostack packs nearly 100 billion transistors onto a piece of silicon the size of a fingernail, close to double the density of the 2 nanometer chip it unveiled in 2021. According to its published technical results, the new node delivers up to 50 percent more performance or up to 70 percent greater energy efficiency compared with that 2 nanometer technology. Those two figures describe opposite ends of the same tradeoff rather than a single chip doing both at once, so a designer could spend the gain on raw speed or on lower power draw depending on what the product needs. For data centers straining under the electricity demands of generative AI, the efficiency option is the one likely to draw the most attention.
The architecture also brings a structural bonus that matters for AI work specifically. By stacking layers, nanostack lets engineers use different material combinations within each layer, tuning every transistor independently for performance or power. In separate research presented at the VLSI 2026 conference, IBM showed the design achieving 40 percent scaling in SRAM, the fast on chip memory that feeds data to processors. Memory bandwidth has become one of the tightest bottlenecks in running large AI models, so a denser, more efficient SRAM cell addresses a problem that pure transistor count alone does not solve.
IBM framed the work as a continuation of a long lead in semiconductor research. “We’re not just making smaller transistors, we’re reinventing how chips are built,” said Jay Gambetta, Director of IBM Research and an IBM Fellow, who called the result a foundation for the next era of computing. The company traces a line from its early semiconductors in the 1960s through the first 2 nanometer node to this sub 1 nanometer demonstration, and it says the nanostack approach gives its roadmap at least another decade of scaling, a notable claim in an industry that has repeatedly been told the end of shrinking was near.
The supporting cast behind the chip points to how such advances now happen. IBM and its partners did the work at a research facility in Albany, New York, which is set to receive a High Numerical Aperture Extreme Ultraviolet lithography tool from ASML, the machine widely seen as essential for printing circuits at these dimensions. Companies including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions are collaborating on the processes and tools, a reminder that no single firm builds a leading edge chip alone. IBM separately said it is forming Anderon, which it describes as the world’s first pure play quantum foundry, signaling ambitions that stretch beyond classical computing.
The important caveat is timing. This is a research demonstration, a proof that the technology can be physically built and can compute, not a product rolling off a production line. IBM says it sees a path to production in as early as the next five years, which means the chips powering phones, laptops, and servers will not feel this for some time, and a great deal of engineering stands between a validated structure in a lab and high volume manufacturing. Breakthroughs at this stage have a way of arriving later and costing more than first projected.
Still, crossing below one nanometer is the kind of marker the industry watches closely, because it answers a question that has hung over computing for years. The relentless doubling of transistor density was supposed to be slowing toward a stop, and each new node has been harder won than the last. By stacking transistors instead of only shrinking them, IBM is arguing that there is still room to grow, and that the era of angstrom scale computing has a real path forward rather than a dead end.
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